Semiconductor devices or integrated circuits (ICs) can include millions of devices, such as, transistors. Ultra-large scale integrated (ULSI) circuits can include complementary metal oxide semiconductor (CMOS) field effect transistors (FET). Despite the ability of conventional systems and processes to fabricate millions of IC devices on an IC, there is still a need to decrease the size of IC device features, and, thus, increase the number of devices on an IC. Nevertheless, there are many factors that make the continued miniaturization of ICs difficult. For example, as the size of vias (or pathways between integrated circuit layers used to electrically connect separate conductive layers) decreases, electrical resistance increases.
Conventional integrated circuits utilize vias to connect structures (e.g., gates, drain regions, source regions) and conductive lines. For example, a via can connect a gate above the substrate to a conductor line in a metal 1 layer. Vias can also interconnect conductive lines. For example, a via can connect a conductive line in a metal 1 layer to a conductor line in a metal 2 layer. A via is typically a metal plug which extends through an insulative layer in a multilayer integrated circuit. Vias and barrier layers are discussed in U.S. Pat. Nos. 5,646,448; 5,770,519; and 5,639,691; each of which are assigned to the assignee of the present application. A barrier layer is used to protect the via and insulative layer from metal diffusion and the via and conductive line from electromigration (EM). The barrier layer can contribute significantly to resistance associated with the via metal. Electromigration is the mass transport due to momentum exchange between conducting electrons and diffusing metal atoms. Electromigration causes progressive damage to the metal conductors in an integrated circuit. In general, metals are most susceptible to electromigration at very high current density and temperatures of 100° C. or more.
Integrated circuit manufacturers have attempted to reduce via resistance as the via size decreases by reducing the thickness of the barrier material. According to a conventional plasma vapor deposition (PVD) process, IC manufacturers deposit a very thin barrier material at the bottom of the via due to non-conformal deposition. The thickness of the barrier material is reduced by chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes. These advanced deposition processes form highly conformal barrier metal films. However, reducing the barrier thickness causes the barrier to become more permeable to copper (Cu) diffusion, which can adversely affect resistance to electromigration.
A conventional integrated circuit can include a copper layer, a copper via, a copper layer, a dielectric layer, and a dielectric layer. The via and copper layer are separated by a barrier layer.
The integrated circuit can also include a dielectric layer that is separated from the copper layer by an etch stop layer. The dielectric layer can be oxide and the etch stop layer can be Silicon Nitride (SiN). The etch stop layer prevents diffusion of copper from the copper layer into the dielectric layer. The dielectric layer can be separated from the copper layer by a barrier layer. Barrier layers can be Tantalum Nitride (TaN). Etch stop layers can be Silicon Nitride (SiN).
According to conventional processes, the barrier layer can have a cross-sectional thickness of between 7 nm to 25 nm. The barrier layer inhibits diffusion of copper ions from layers into the via and from the via into the dielectric layer. Conventional barrier layers can include Tantalum Nitride (TaN).
As discussed above, conventional systems have attempted to reduce the thickness of the barrier layer to reduce the resistance associated with the via. However, this reduction in thickness can cause electromigration failures.
Electromigration failures have been described by Stanley Wolf, Ph.D. in Silicon Processing for the VLSI Era, Lattice Press, Sunset Beach, Calif., Vol. 2, pp. 264-65 (1990). Dr. Wolf explains that a positive divergence of the motion of the ions of a conductor leads to an accumulation of vacancies, forming a void in the metal. Such voids may ultimately grow to a size that results in open-circuit failure of the conductor line.
Thus, there is a need for a barrier that is more resistant to copper diffusion. Further, there is a need for a method of forming an adhesion layer with an element reactive with a barrier layer to improve resistance to copper diffusion. Even further, there is a need for a method of enhancing barrier properties by providing an adhesion layer as an interfacial layer between a barrier layer and a copper layer.